This is an implemetation of an LZW encoder in SystemC which has been verified by implementing a test bench and requisite test vectors. Only those constructs of SystemC have been used which are synthesizabe abd recognized by the "SC2V" converter. It has than been converted to Verilog code by using the open source "SC2V" program. The converted RTL is again verified in verilog simulations, and then verified in a Xilinx FPGA. The Digilent Spartan3 system board was used to verify the LZW code.
DOC
The doc folder contains a document which describes the LZW implementation, as well as the testbench implementation
SystemC
The systemc folder contains the LZW implementation files in SystemC format. This is synthesizable SystemC code.
SystemC Models
The systemc_models folder contains the serial port, model used in simulation, which is implemented in systemC
SystemC Test Bench
The systemc_tb folder contains the testbench for simulation in SystemC format.
Converted Verilog RTL
The converted_verilog_rtl folder contains the LZW rtl files, converted from systemC using the SC2V open source converter. A C-Shell script "sc2v.sh" is present to convert all SystemC synthesizable files to Verilog format.
Verilog Models
The verilog_models folder contains the serial port model used in simulation.
The following RAM models can be obtained from Xilinx ISE web pack for
simulation purposes.
RAMB4_S8.v
RAMB4_S8_S8.v
RAMB16_S18.v
RAMB16_S18_S18.v
Verilog Test Bench
The verilog_tb folder contains the testbench for simulation in verilog format, for testing the converted code.
Verilog Test Cases
The verilog_test_cases contains the test files used for RTL simulations
Run
The run folder contains a sample "run.do" file to run the verilog simulations in Modelsim
FPGA Bit Files
The fpga_ucf_bit folder contains the UCF file for FPGA implementation, as well as the bit and mcs file
FPGA Test Files
The fpga_test_files folder contains the files which are downloaded into the FPGA for compressing, through "braypp" serial port program. This is freely available on the net. input test files in1.txt, in2.txt, in3.txt